The present invention relates to semiconductor devices, such as flash electrically erasable and programmable read only memory (EEPROM) cell structures, and processes for making them, and more particularly to a bird""s beak free isolation technology for memory cell structures.
In the development of non-volatile semiconductor memory devices of the types such as erasable (EPROM), electrically erasable (EEPROM), and flash EEPROM devices, it is currently a goal to provide an array of a great number of individual memory cells on a single silicon integrated circuit chip of practical size. This trend requires failure free isolation technology to physically and electrically separate neighboring memory elements (memory cells) and peripheral control circuit elements. Currently, an electrically insulating layer is employed for this purpose.
A silicon substrate area occupied by active elements (memory elements and peripheral circuit elements) may be called an xe2x80x9cactive element region,xe2x80x9d and a silicon substrate area occupied by an electrically insulating layer a xe2x80x9cneighboring elements separating region or separating region.xe2x80x9d An electrically insulating layer that is grown on the separating region may be called a xe2x80x9cneighboring elements separating insulating layer.xe2x80x9d Currently, the insulating layer is grown over each of the separating regions on the semiconductor (silicon) substrate by LOCOS (local oxidation) technique. Specifically, an oxide layer, with a thickness of around 50 nanometers (nm) of silicon dioxide and a silicon nitride layer with a thickness of around 100 to 400 nanometers (nm) are grown onto the substrate to form a sandwich structure. Optical lithography and dry etching techniques remove portions of the silicon nitride layer extending over the separating regions. After removing the portions of the silicon nitride layer, thermal oxidation grows an oxide layer that forms the separating insulating layer.
The LOCOS technique involves a bird""s beak problem, which limits the scaling down of the cell array structure.
U.S. Pat. No. 5,595,924 (issued on Jan. 21, 1997 to Yuan et al.) teaches a technique of forming a cell array structure with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a practical size. The technique employs three processing steps. The first step is to deposit a silicon dioxide layer on a silicon substrate by CVD. The second or next step is to etch away portions of silicon dioxide layer over active regions by optical lithography and dry etching techniques. The third step is to form spacers of silicon dioxide along the sidewall of each opening in the etched silicon dioxide layer.
FIGS. 5A through 5E illustrate processing steps employed by the known technique disclosed by the above-mentioned patent. In FIG. 5A, an oxide layer 501 of silicon dioxide is deposited on a silicon substrate 500 by CVD. In FIG. 5B, optical lithography technique forms a resist 502 over each of separating region. In FIG. 5C, dry etching technique etches away, using the resists 502 as a mask, portions of oxide layer that extend over active element regions. Subsequently, the resists 502 are removed. As shown in FIG. 5C, the edges of the etched oxide layer 501 have essentially vertical profiles. In FIG. 5D, low-pressure CVD deposits an oxide layer 503 over the entire surface of the etched oxide layer 501 and the exposed areas of the silicon substrate. In FIG. 5E, anisotropic dry etching technique remove all of the oxide layer 503 leaving portions on the edges of the etched oxide layer 501 as spacers 504 along the sidewall of each opening in the etched oxide layer 501.
Processing steps as illustrated in FIGS. 5D and 5E may be replaced by a single processing step of anisotropic etching the oxide layer 501 so that the edges of the etched oxide layer 501 have slightly tapered profile as shown in FIG. 6C at 601. FIGS. 6A and 6B correspond to FIGS. 5A and 5B, respectively.
U.S. Pat. No. 5,343,063 (issued on Aug. 30, 1994 to Yuan et al.), which appears to correspond to JP-A 4-340767 published on Nov. 27, 1992, discloses a memory array of PROM, EPROM or EEPROM cells. Each cell is formed in a trench of a thick oxide layer that is deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell, which provide capacitive coupling between them, are formed vertically. This allows the density of the array to be increased. This is because the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of forming capacitive coupling.
FIGS. 7 and 8 are a plan view and a sectional view taken along the line 8xe2x80x948 of the plan view illustrating a flash EEPROM device to which the present invention has been applied.
Each memory cell has an embedded diffusion layer (BN+) as a bit line, and employs a laminated structure of the floating gate, control gate and erase gate. In FIGS. 7 and 8, the reference numeral 700 designates a silicon substrate of the P-type, and the reference numeral 701 designates an oxide layer of silicon dioxide, which forms separating regions. The reference numeral 702 designates active regions. The reference numeral 703 designates auxiliary bit lines. The reference numeral 704 designates floating gates. The reference numeral 705 designates control gates serving as word lines. The reference numeral 706 designates erase gates. The reference numeral 707 designates a first gate-insulating layer formed on the silicon substrate 700. The reference numeral 708 designates a second gate-insulating layer between the adjacent floating and control gates 704 and 705. The reference numeral 709 designates a third gate-insulating layer between the adjacent floating and erase gates 704 and 706. The reference numeral 710 designates an insulating layer electrically separating the control and erase gates 705 and 706 from each other. The reference numeral 711 designates gates of transistors within the peripheral circuit region. The reference numeral 712 designates an interlayer insulating layer. The reference numeral 713 designates main bit lines for memory cells. The reference numeral 714 designates contacts.
Manufacturing the flash EEPROM devices as illustrated in FIGS. 7 and 8 requires a number of oxidation processes after forming the gates. For example, after forming the floating gates, thermal oxidation processes are required to deposit the second gate-insulating layer 708 and the third gate-insulating layer 709. An oxide layer is deposited over the surface of the silicon substrate by thermal oxidation to protect the substrate surface from contamination prior to various ion implantation operations into source and drain regions of the peripheral transistors. In the oxidation processes, oxygen radical created within a furnace easily diverges through the separating regions in the form of silicon dioxide and reaches the floating gate of each memory cell, the transfer gate of each memory cell and the gate of each peripheral transistor, thereby oxidizing the silicon substrate and the material of the gates. This encroachment of the oxide into the bottom of the floating gate of each memory cell, the transfer gate of each memory cell and the gate of each transistor is known as a xe2x80x9cgate bird""s beakxe2x80x9d because of its shape when viewed in cross-section.
This bird""s beak causes the amount of ON-current of each memory cell or each peripheral transistor to drop appreciably. This is because the CVD deposited oxide layer that forms the separating insulating layer has poor oxidation proof, thereby allowing oxygen radical to reach the interface between the gate, gate-insulating layer and silicon substrate. This results in increased thickness of the gate-insulating layer.
Another problem posed by the bird""s beak is to provide a limitation to scaling down of each memory cell. This is because the bird""s beak narrows the effective channel width as compared to the designed one. Since the amount or size of the bird""s beak is inherently determined by the process of manufacturing the devices, its influence upon width of the effective channel gradually increases as the size of each memory cell decreases.
An object of the present invention to provide a semiconductor device which has eliminated or reduced the bird""s beak, thereby making it possible to scaling down of the size of each memory cell and each peripheral transistor, and a process of making it.
According to one aspect of the present invention, there is provided a semiconductor device including adjacent elements separated by an electrically insulating layer, wherein said insulating layer has a portion that has an oxidation proof property.
According to another aspect of the present invention, there is provided a process of making a semiconductor device, comprising the steps of:
forming a sandwich structure on a semiconductor substrate by laminating a first oxide layer, a nitride layer and a second oxide layer;
depositing, by optical lithography, a photo resist extending over each neighboring elements separating region; and
removing, by dry etching using said photo resist as a mask, portions of said sandwich structure that extend over active regions.
According to still another aspect of the present invention, there is provided a process of making a semiconductor device comprising the steps of:
forming an oxide layer on a semiconductor substrate;
depositing, by optical lithography, a photo resist extending over each neighboring elements separating region;
removing, by dry etching using said photo resist as a mask, portions of said oxide layer that extend over active regions to define openings; and
depositing, by CVD, a nitride layer over said etched oxide layer and the exposed semiconductor substrate; and
removing, by anisotropically etching, said nitride layer leaving portions extending along the sidewall of the openings, in said etched oxide layer.